Implementation of Area Efficient and High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters

Suda Sriram, Ch. Kanakalingeswara Rao


Traditional Serial-Serial multiplier addresses the high data sampling rate. It is effectively considered as the entire partial product matrix with n data sampling cycle for n×n multiplication function instead of 2n cycles in the conventional multipliers. This multiplication of partial products by considering two series inputs among which one is starting from LSB the other from MSB. Using this feed sequence and accumulation technique it takes only n cycle to complete the partial products. It achieves high bit sampling rate by replacing conventional full adder and highest 5:3 counters. Here asynchronous 1’s counter is presented. This counter takes critical path is limited to only an AND gate and D flip-flops. Accumulation is integral part of serial multiplier design. 1’s counter is used to count the number of ones at the end of the nth iteration in each counter produces. The implemented multipliers consist of a serial-serial data accumulator module and carry save adder that occupies less silicon area than the full carry save adder. In this paper we implemented model address for the 8bit 2’s complement implementing the Baugh-wooley algorithm and unsigned multiplication implementing the architecture for 8×8 Serial-Serial unsigned multiplication


Binary multiplication, on-the-fly accumulation, parallel multipliers, serial and serial-parallel multiplier.


Meher MR,Ching Chuen Jong; Chip Hong Cheng , “A High bit rate Serial-Serial multiplier”,IEEE Trans.VLSI,vol.19,pp.1733-1745,Sept 2010

Essam Elsayed and Hatem M. El-Boghdadi “Area-Time Efficient Digit-Serial-Serial Two’s Complement Multiplier” Vol. 2, Special Issue 1, Part 2, February 2009.

OHSANG KWON and KEVIN NOWKA “A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells” Journal of VLSI Signal Processing 31, 77–89, 2009.

P. Assady “A New Multiplication Algorithm Using High-Speed Counters” European Journal of Scientific Research ISSN 1450-216X Vol.26 No.3 (2009), pp.362-368.

Harpreet Singh Dhillon and Abhijit Mitra “A Reduced-Bit Multiplication Algorithm for Digital Arithmetic” International Journal of Computational and Mathematical Sciences 2:2 2008

Ravi Nirlakalla, Thota Subba Rao, Talari Jayachandra Prasad, “Performance Evaluation of High Speed Compressors for High Speed Multipliers” Vol. 8, No. 3, November 2006, 293-306

Nibouche.O, Bouridarie.A, and Nibouche.M (2001), ‘New architectures for serial-serial multiplication’ in Proc. IEEE Conf. Circuits Syst. (ISCAS), Sydney, Australia, vol. 2, pp. 705–708.

H. K. Mecklai and A. L.Webb, “Compact buffer design for serial I/O”U.S. Patent 6 167 109, Dec. 26, 2000.

Sungwook Kim and Gerald E. Sobelman, “Digit-Serial Multiplier Design Using Skew-Tolerant Domino Circuits” University of Minnesota Minneapolis, MN 55454, USA (2000).

Sumit Vaidya and Deepak Dandekar “Delay-Power Performance Comparison Of Multipliers In Vlsi Circuit Design” International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4,


J.Senthil Kumar G.Lakshminarayanan “Design and Implementation of FPGA based Fast Multipliers with Optimum Placement and Routing using Structure Organizer” Department of ECE, Regional Engineering College, Tiruchirapalli.

0. Nibouche.O, A. Bouridarie, M. Nibouche.O “New Architectures for Serial-Serial Multiplication” 0-7803-6685-9101/$10.0002000 IEEE.

A AGGOUN, A ASHUR and M K IBRAHIM “Area-Time Efficient Serial-Serial Multipliers” ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland.

Paolo Ienne and Marc A. Viredaz “Bit-Serial Multipliers and Squarers” IEEE Transactions on Computers. vol. 43, no. 12, December 1994.

R. GNANASEKARAN “On a Bit-Serial Input and Bit-Serial Output Multiplier” IEEE Transactions on Computers, VOL. C-32, NO. 9, September 1983

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