Rtl Desing And Vlsi Implementation Of An Efficient Convolution Encoder And Adaptive Viterbi Decoder

Abstract

Error-correcting convolution codes provide a proven mechanism to limit the effects of noise in digital data transmission. Convolution codes are employed to implement forward error correction(FEC) but the complexity of corresponding decoders increases exponentially with the constraint length K. Convolution Encoding with Viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive white Gaussian Noise. In this paper, we present a Convolution Encoder and Viterbi Decoder with a constraint length of 9 and code rate of 1/2. This is realized using Verilog HDL. It is simulated and synthesized using Modelsim Altera 10.0d and Xilinx 12.1 ISE. The main aim of this paper is to design based Convolution Encoder and Viterbi Decoder which encodes/decodes the data. This architecture has simpler code and flexible configuration when compared to other architectures and saves silicon area through efficient device utilization which makes it favorable for fpga.