Email this article Carbon Nanotube based approach on FETs using Ternary Comparator
Abstract
A Carbon Nanotube Field Effect Transistor (CNFET) is referred to as a FET that utilizes a single Carbon Nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. New approach of ternary magnitude comparator based on the CNFET ternary logic gates. These gates are promising alternative to conventional logic design because of its energy efficiency, it can accomplish by the reduced circuit on ternary logic. Ternary comparator implementation is based on prefix based design and combines ternary and binary logic gates for optimized implementation. A novel approach of a comparator has been implemented and simulated using SPICE. A design response indicates that the 1-bit comparator consumes less power say 0.65µW and has a delay of 21ps. The simulation results for comparators with versatile lengths of operands.
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References
M. Mukaidono, “Regular ternary logic functions—Ternary logicfunctions suitable for treating ambiguity,” IEEE Trans. Comput., vol. C35,no.2,pp.179–183,Feb.1986.
P. C. Balla and A. Antoniou, “Low power dissipation MOS ternary logic family,” IEEE J. Solid-State Circuits, vol. 19, no. 5, pp. 739–749, Oct. 1984.
A. Heung and H. T.Mouftah, “Depletion/enhancement CMOS for alower power family of three-valued logic circuits,” IEEE J. Solid-State Circuits, vol. 20, no. 2, pp. 609–616, Apr. 1985.
A. Raychowdhury and K. Roy, “Carbon-nanotube-based voltage-mode multiple-valued logic design,” IEEE Trans. Nanotechnology., vol. 4, no. 2, pp. 168–179, Mar. 2005.
D. A. Rich, “A survey of multivalued memories,” IEEE Trans. Computer.,vol. 35, no. 2, pp. 99–106, Feb. 1986.
Y. Yasuda, Y. Tokuda, S. Taima, K. Pak, T. Nakamura, and A. Yoshida,“Realization of quaternary logic circuits by n-channel MOS devices,”IEEE J. Solid-State Circuits, vol. 21, no. 1, pp. 162–168, Feb. 1986.
J. Appenzeller, “Carbon nanotubes for high-performance electronics—Progress and prospect,” Proc. IEEE, vol. 96, no. 2, pp. 201–211, Feb. 2008.
H. Hashempour and F. Lombardi, “Device model for ballistic CNFETs using the first conducting band,” IEEE Des. Test. Comput., vol. 25, no. 2, pp. 178–186, Mar./Apr. 2008.
Sheng Lin; Yong-Bin Kim; Lombardi, F.; , "CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits," IEEE Transactions on Nanotechnology, vol.10, no.2, pp.217-225, March 2011.
S. Lin, Y.-B. Kim, and F. Lombardi, “A novel CNTFET-based ternarylogic gate design,” in Proc. IEEE Int. Midwest Symp. Circuits Syst., Aug. 2009, pp. 435–438.
(2008). Stanford University CNFET model Website. StanfordUniversity, Stanford, CA [Online]. Available:
http://nano.stanford.edu/model.php?id=23
J. Deng and H.-S.P.Wong, “A compact SPICE model for carbon nanotube field-effect transistors including nonidealities and its application —PartI:Model of the intrinsic channel region,”IEEETrans.ElectronDevice,vol.54,no.12,pp.3186–3194,Dec. 2007.
J. Deng and H.-S.P.Wong, “A compact SPICE model for carbonnanotubefield-effect transistors including non idealities and its application—PartII:Full device model and circuit performance bench marking, ”IEEETrans. Electron Device, vol.54, no.12, pp.3195–3205, Dec.2007.
Y. Ohno, S. Kishimoto, T. Mizutani, T. Okazaki, and H. Shinohara,“Chirality assignment of individual single-walled carbon nanotubes in carbon nanotube field-effect transistors by micro-photo current spectroscopy,” Appl. Phys. Lett., vol. 84, no. 8, pp. 1368–1370, Feb.2004.
B.Wang, P. Poa, L.Wei, L. Li, Y. Yang, and Y. Chen, “(n,m) Selectivity of single-walled carbon nanotubes by different carbon precursors on Co–Mo catalysts,” J. Amer. Chem. Soc., vol. 129, no. 9, pp. 9014–9019,2007.
Perri, S.; Corsonello, P.; , "Fast Low-Cost Implementation of Single Clock-Cycle Binary Comparator," Circuits and Systems II:Express Briefs, IEEE Transactions on, vol.55 no.12, pp.1239-1243, Dec.2008.
A. P. Dhande and V. T. Ingole, “Design&Implementation of 2-BitTernary ALU slice,” in Proc. Int. Conf. IEEE-Sci. Electron., Technol.Inf. Telecommun., Mar. 2005, pp. 17–21.
ChetanVudadha, SaiPhaneendra P, GouthamMakkena, Sreehari V, N Moorthy Muthukrishnan, M B Srinivas Department of EEE,BITS-Pilani, “Digital System Design” IEEE conference, 2012.
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