Area and Power efficient booth’s Multipliers Based on Non-Redundant Radix-4Signed-Digit Encoding

R Bheema Sankaram, P Gopalaswamy


In this paper, we introduce an architecture of pre-encoded multipliers for Digital Signal Processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values {-1, 0, +1, +2} or {-2,-1,0,+1}, is proposed leading to a multiplier design with less complex partial products implementation. Extensive experimental analysis verifies that the proposed pre-encoded NR4SD multipliers, including the coefficients memory, are more area and power efficient than the conventional Modified Booth scheme.


Multiplying circuits, Modified Booth encoding, Pre-Encoded multipliers, VLSI implementation.


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