Various Power Dissipation Mechanisms and Leakage Current Reduction Techniques in Deep-Submicron Technology

D. Sudhakar, R. Durga Bhavani

Abstract


Power consumption is a major issue in today’s VLSI technology. Earlier power consumption was of secondary concern. In nanometre technology power has become the important issue because increasing transistor count, higher speed of operation, greater leakage currents. Power dissipation is proportional to speed of operation. With shrinking transistor size and technology, reducing power dissipation and over all power management on chip are the key challenges below 100nm. For many designs, reduction of power dissipation is an important issue due to the need to reduce packaging and cooling cost, extended battery life. For power management leakage power also plays an important role in low power VLSI designs. Leakage power increases at a faster rate than dynamic power in technology generation. This paper describes about the various power dissipation methods along with leakage power management techniques for low power VLSI circuits and systems.

Keywords


VLSI, Dynamic power dissipation, Static power dissipation, CMOS inverter, Variable threshold voltage, Power Gating, MTCMOS, Leakage Control Transistor.

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