Power Aware and Density Optimized High Fan-in Posit-HUB Using Modified CSLA

Abstract

In recent years, the posit number system has gained attention as a promising alternative to the traditional IEEE floating-point representation, especially within the field of deep learning. Thanks to its non-uniform distribution of values, the posit format aligns more closely with the data characteristics observed in deep learning models. This advantage enables faster training and improved computational efficiency. Among various arithmetic operations, multiplication is one of the most frequently used in these applications. To address the hardware complexity associated with such operations, the HUB (Hybrid Unum Binary) approach, introduced in 2016, focused on reducing the cost of floating-point hardware units. Building upon this idea, a novel format known as the HUB posit has been proposed. This format aims to further decrease the hardware overhead typically found in posit arithmetic units. Specifically, this research introduces a power-efficient posit adder architecture. While the mantissa adder is still designed to accommodate the maximum possible bit-width, the architecture cleverly segments the adder into several smaller units. These smaller adders operate based on the regime bit-width, which effectively determines the required mantissa bit-width for a given operation. This design methodology is implemented and tested on both 6-bit and 11-bit posit configurations. Moreover, the architecture is enhanced by incorporating a modified carry select adder along with Binary Excess Converters. This enhancement significantly optimizes the performance by reducing both power consumption and processing delay, making it well-suited for efficient and scalable deep learning hardware solutions.