Low-Error and High-Throughput Discrete Cosine Transform (DCT) Design

Sadiq Ali Mohammad, Sumanth K

Abstract


In this paper, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design.  Many DCT architectures were proposed on systolic design to reduce the number of multipliers in the systolic design as multipliers consumes high power and occupy less area . Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise-ratio (PSNR) requirements. He proposed 2-D DCT core synthesized by usingXilinx ISE 9.1, and the Xilinx XC2VP30 FPGA can achieve 792 megapixels per second (M-pels/sec) throughput rate.

Keywords


Distributed arithmetic (DA)-based, error-compensated adder-tree (ECAT), 2-D discrete cosine transform (DCT).

References


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