A High speed Vedic Multiplier using Different Compressors

Devi Sasikala D, Nagaraju NV


With the advent of new technology in the ields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.


4:2 Compressor, 7:2 Compressor, Booth’s Multiplier, High Speed Multiplier, Modiied Booth’s Multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics


Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, “Vedic Mathematics: Sixteen Simple Mathematical Formulae from the Veda”.

L. Sriraman, T.N. Prabakar,“Design and Implementation of Two Variable Multiplier Using KCMand Vedic Mathematics”, 1st Int. Conf. on RecentAdvances in Information Technology, Dhanbad, India, 2012, IEEE Proc., pp. 782-787.

C. R. Baugh, B. A. Wooley,“A Two’s Complement Parallel Array Multiplication Algorithm”, IEEE Trans. Computers 22(12), pp. 1045–1047, 1973.

Himanshu Thapliyal, M. B. Srinivas,“An eficient method of elliptic curve encryption using Ancient Indian Vedic Mathematics”, 48th IEEE Int. Midwest Symp. on Circuits and Systems, 2005, Vol. 1, pp. 826-828.

A.D.Booth,“A Signed Binary Multiplication Technique”,

J. mech. And appl. math, Vol 4, No.2, pp. 236-240, Oxford

University Press, 1951.

M. Ramalatha, K. Deena Dayalan, S. Deborah Priya, “High Speed Energy Eficient ALU Design using Vedic Multiplication Techniques”, Advances in Computational Tools for Engineering Applications, 2009, IEEE Proc., pp. 600-603.

L. Ciminiera, A. Valenzano,“Low cost serial multipliers for highspeed specialised processors”, Computers and Digital Techniques.

Koren Israel,"Computer Arithmetic Algorithms”, 2nd Ed, pp. 141-149, Universities Press, 2001.

Tiwari, Honey Durga, et al.,“Multiplier design based on ancient Indian Vedic Mathematics", Int. SoC Design Conf., 2008, Vol. 2. IEEE Proc., pp. II-65 - II-68.

Hsiao, Shen-Fu, Ming-Roun Jiang, Jia-Sien Yeh,“Design of highspeed low-power 3-2 counter and 4-2 compressor for fast multipliers”, IEEE Electronics Letters, Vol. 34, No. 4, pp. 341-343, Feb. 1998



  • There are currently no refbacks.

Copyright © 2013, All rights reserved.| ijseat.com

Creative Commons License
International Journal of Science Engineering and Advance Technology is licensed under a Creative Commons Attribution 3.0 Unported License.Based on a work at IJSEat , Permissions beyond the scope of this license may be available at http://creativecommons.org/licenses/by/3.0/deed.en_GB.