Design and Implementation of Unsigned Multiplier Using COSA

Abstract

In this paper, design of COSA multiplier is presented, by introducing Carry Save Adder (CSA) in partial product lines. The multiplier given in this paper is modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The four binary adder architectures belong to a different adder class based 32-bit unsigned integer multiplier. The four binary adder architectures are Ripple carry adder (RCA), Carry Look-ahead adder (CLAA), Carry Select adder (CSLA) and Conditional Sum adder (COSA). All these multipliers multiply two 32-bit unsigned integer values and give a product term of 64-bit values. A system’s performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the systemThis work evaluates the performance of the proposed designs in terms of delay, speed(frequency)and memory.