Various Power Dissipation Mechanisms and Leakage Current Reduction Techniques in Deep-Submicron Technology

D. Sudhakar, R. Durga Bhavani


Power consumption is a major issue in today’s VLSI technology. Earlier power consumption was of secondary concern. In nanometre technology power has become the important issue because increasing transistor count, higher speed of operation, greater leakage currents. Power dissipation is proportional to speed of operation. With shrinking transistor size and technology, reducing power dissipation and over all power management on chip are the key challenges below 100nm. For many designs, reduction of power dissipation is an important issue due to the need to reduce packaging and cooling cost, extended battery life. For power management leakage power also plays an important role in low power VLSI designs. Leakage power increases at a faster rate than dynamic power in technology generation. This paper describes about the various power dissipation methods along with leakage power management techniques for low power VLSI circuits and systems.


VLSI, Dynamic power dissipation, Static power dissipation, CMOS inverter, Variable threshold voltage, Power Gating, MTCMOS, Leakage Control Transistor.


. Strategies & Methodologies for low Power VLSI Designs: A Review(IJAET-2011).

. Peiyi Zhao, Jason McNeely, Weidong Kuang, Nan Wang, and Zhongfeng Wang,“Design of Sequential Elements for Low Power Clocking System” in IEEE VLSI Systems, vol. 19, no. 5, May 2011.

. Farzan Fallah, Massoud Pedram “Standby and Active Leakage Current Control and Minimization” in CMOS VLSI Circuits”

. Kanika Kaur, Arti Noor, “CMOS Low Power Cell Library for Digital Design”in International Journal VLSICS Vol.4, No.3, June 2013.

. Kaushik Roy, Saibal Mukhopadhyay and

hamid mahmoodi-meimand “Leakage Current Mechanisms and LeakageReduction Techniques in Deep-Submicrometer CMOS Circuits”in IEEE, Vol. 91, no. 2, Feb 2003.

. J. Kao, S. Narendra, and A. Chandrakasan, “Subthreshold Leakage Modeling and eduction Techniques," In Proceedings of the International Conference on Computer Aided Design, pp.141-148, 2002.

. J. Brews, High Speed Semiconductor Devices, Wiley, New York, 1990.

. S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, McGraw-Hill, New York, 2003.

. M. Bohr and et al., “A high-performance 0.25μm logic technology optimized for 1.8V operation," In Proceedings of the International Electron Devices Meeting, pp. 847-850, 1996.

. D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, “Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage" In Proceedings of the 40th Design Automation Conference, pp. 175-180, Anaheim, 2003.

. Y. C. Yeo, “Direct tunneling gate leakage current in transistors with ultra thin silicon nitride gate dielectric," IEEE Transactions on Electron Devices, pp. 540-542, 2000.

. A. Ono and et al., “A 100nm node CMOS technology for practical SOC application requirement," In Proceedings of the International Electron Devices Meeting, pp. 511-514, 2001.

. Wenxin Wang, “Low-Power Multi-Threshold CMOS Circuits Optimization and CAD Tool Design”.

. Prof.Ajit Pal, Department of CSE, IITK

“Introduction and Course Outline” In IEP-10.

. Prof.Ajit Pal, Department of CSE, IITK “Minimizing Leakage Power”In IEP-10.

. B. Dilip, P. Surya Prasad& R.S.G. Bhavani”Leakage Power Reduction in CMOS Circuits using Leakage Control Transistor Technique in Nanoscale Technology”.

] P. Verma, R. A. Mishra, “Leakage power and delay analysis of LECTOR based CMOS circuits”, Int’l conf. on computer & communication technology ICCCT 2011.

H. Narender and R. Nagarajan, “LECTOR: A technique for leakage reduction in CMOS circuits”, IEEE trans. On VLSI systems, vol. 12, no. 2, Feb. 2004.

. M. C. Johnson, D. Somasekhar, L. Y. Chiou, and K. Roy, “Leakage control with efficient use of transistor stacks in single threshold CMOS,”IEEE Trans. VLSI Syst.,vol.10, pp. 1–5, Feb. 2002.

. Bagadi Madhavi, G Kanchana, Venkatesh Seerapu “Low power and area efficient design of VLSI Circuts” in IJSRP, Vol 3, Issue 4, April 2013

Full Text: PDF [FULL TEXT]


  • There are currently no refbacks.

Copyright © 2013, All rights reserved.|

Creative Commons License
International Journal of Science Engineering and Advance Technology is licensed under a Creative Commons Attribution 3.0 Unported License.Based on a work at IJSEat , Permissions beyond the scope of this license may be available at