Email this article Low Complexity Reliability Based Message Passing Decoder Architecture For Non Binary LDPC Codes
Abstract
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the codeword length is moderate. The recently developed iterative reliability-based majority-logic NB-LDPC decoding has better performance complexity tradeoffs than previous algorithms. This paper first proposes enhancement schemes to the iterative hard reliability-based majority-logic decoding (IHRB-MLGD). Compared to the IHRB algorithm, our enhanced (E)-IHRB algorithm can achieve significant coding gain with small hardware overhead. Then low-complexity partial-parallel NB-LDPC decoder architectures are developed based on these two algorithms. Moreover, novel schemes are developed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. In addition, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NB-LDPC codes. our proposed decoders have at least tens of times lower complexity with moderate coding gain loss.
Keywords
References
L. Barnault and D. Declercq, “Fast decoding algorithm for LDPC over,” in Proc. Inf. Theory Workshop, 2003, pp. 70 –73.
H. Wymeersch, H. Steendam, and M. Moeneclaey, “Log-domain decoding of LDPC codes over ,” in Proc. IEEEInt. Conf. Commun., 2004, pp. 772–776.
C.Spagnol, E.Popovici, and W. Marnane, “Hardware implementation of LDPC decoders,” IEEE Trans.Circuits Syst.I, Reg. Papers, vol. 56, no. 12, pp. 2609–2620, Dec. 2009.
D. Declercq and M. Fossorier, “Decoding algorithms for non binary LDPC codes over ,” IEEE Trans. Commun., vol. 55, no. 4, pp. 633–643, Apr. 2007.
. V.Savin,“ Min-Max decoding for non binary LDPC codes,” in Proc. IEEE Int. Symp. Inf. Theory, 2008, pp. 960–964.
.J.Lin, J.Sha, Z.Wang, and L.Li, “An efficient VLSI architecture for non binary LDPC decoders, ”IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 1, pp. 51–56, Jan. 2010.
J.Lin, J.Sha ,Z.Wang, andL.Li, “Efficient decoder design for non-binary quasi cyclic LDPC codes, ” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 5, pp. 1071–1082, May 2010.
X.Zhang and F.Cai, “Efficient partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 28, no. 2, pp. 402–414, Feb. 2011.
X. Zhang and F. Cai, “Reduced-complexity decoder architecture for non-binary LDPC codes,”IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 7, pp. 1229–1238, Jul. 2011
Refbacks
- There are currently no refbacks.
Copyright © 2013, All rights reserved.| ijseat.com
International Journal of Science Engineering and Advance Technology is licensed under a Creative Commons Attribution 3.0 Unported License.Based on a work at IJSEat , Permissions beyond the scope of this license may be available at http://creativecommons.org/licenses/by/3.0/deed.en_GB.