Low Latency Mac Design For Low Power DSP Applications

Kadali Swathi, M Srihari


In this work a rapid and vitality productive two-cycle duplicate gather (MAC) engineering that backings both marked and unsigned numbers is proposed. A productive MAC configuration utilizing 4:2 compressors is displayed in this idea. In this paper, a low-control rapid 4:2 compressor circuit is proposed for quick computerized math coordinated circuits. Macintosh comprises multiplier and viper units. The 4:2 compressor has been generally utilized for multiplier acknowledge. This multiplier utilizes another halfway item diminishment arrange which sequentially decreases the most extreme yield delay. This undertaking is upgraded by utilizing baugh-wooley multiplier for inertness change. Baugh-wooley multiplier does its augmentation in two's compliment shape.


Chang, Chip-Hong, Jiangmin Gu, and Mingyan Zhang. "Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits." Circuits and Systems I: Regular Papers, IEEE Transactions on 51.10 (2004): 1985-1997.

Tung Thanh Hoang; Sjalander, M.; Larsson-Edefors, P., "A High-Speed, Energy-Efficient Two-Cycle Multiply Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.57, no.12, pp.3073,3081, Dec. 2010.

Chen Ping-hua; Zhao Juan, "High-speed Parallel 32×32-b Multiplier Using a Radix-16 Booth Encoder," Intelligent Information Technology Application Workshops, 2009. IITAW '09. Third International Symposium on , vol., no., pp.406,409, 21-22 Nov. 2009

Kiwon Choi; Minkyu Song, "Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder," Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , vol.2, no., pp.701,704 vol. 2, 6-9 May 2001.

Rajput, R.P.; Swamy, M.N.S., "High Speed Modified Booth Encoder Multiplier for Signed and Unsigned Numbers," Computer Modelling and Simulation (UKSim), 2012 UKSim 14th International Conference on , vol., no., pp.649,654, 28-30 March 2012.

Yangbo Wu; Weijiang Zhang; Jianping Hu, "Adiabatic 4-2 compressors for low-power multiplier," Circuits and Systems, 2005. 48th Midwest Symposium on , vol., no., pp.1473,1476 Vol. 2, 7-10 Aug. 2005.

Jaina, D.; Sethi, K.; Panda, R., "Vedic Mathematics Based Multiply Accumulate Unit," Computational Intelligence and Communication Networks (CICN), 2011 International Conference on, vol., no., pp.754,757, 7-9 Oct. 2011.

Aliparast, Peiman, Ziaadin D. Koozehkanani, and Farhad Nazari. "An Ultra High Speed Digital 4-2 Compressor in 65-nm CMOS." International Journal of Computer Theory & Engineering 5.4 (2013).

N. Weste and David Harris, “CMOS VLSI Design- A Circuits & System Perspective”, Pearson Education, 2008.

ChandraMohan U, “Low Power Area Efficient Digital Counters”, Proceedings of the 7th VLSI Design and Test Workshops, VDAT, August 2003.

Narendra C P & Ravi K M Kumar, “Efficient Comparator based Sum of Absolute Differences Architecture for Digital Image Processing Applications”, Foundation of Computer Science, New York, USA, International Journal of Computer Applications, 96(4):17-24, June 2014.

W.-C. Yeh, “Arithmetic Module Design and its Application to FFT,” Ph.D. dissertation, Dept. Electron. Eng., National Chiao-Tung University, , Chiao-Tung, 2001.

R. Zimmermann and D. Q. Tran, “Optimized synthesis of sum-of-products,” in Proc. Asilomar Conf. Signals, Syst. Comput., Pacific Grove, Washington, DC, 2003, pp. 867–872.

B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford: Oxford Univ. Press, 2000.

O. L. Macsorley, “High-speed arithmetic in binary computers,” Proc. IRE, vol. 49, no. 1, pp. 67–91, Jan. 1961.

N. H. E. Weste and D. M. Harris, “Datapath subsystems,” in CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed. Readington: Addison-Wesley, 2010, ch. 11.

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