Email this article Efficient LUT Based Filter Design Using Approximate Algorithm
Abstract
The filter design optimization (FDO) issue is described as finding a strategy of channel coefficients that yields a channel format with scarcest whimsies, fulfilling the channel destinations. It has gotten a mammoth energy by virtue of the regardless of what you look like at it usage of channels. Enduring that the coefficient duplications in the channel course of action are perceived under a move joins fabricating, the adaptable quality is for the most part depicted like the aggregate number of adders and subtractors. In this paper, i exhibit a privilege FDO is upgraded by utilizing Look UP Table approach. APC and OMS paired properties are utilized for actualizing LUT based FIR channel by utilizing APC And OMS decreased the quantity of capacity components right around half. This technique has better execution and it devours less power and possess less space contrast with FDO strategy.
References
L.Wanhammar, DSP Integrated Circuits. New York, NY, USA: Academic, 1999.
H.Nguyen andA. Chatterjee, “Number-splittingwith shift-and-add decomposition for power and hardware optimization in linear DSP synthesis,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 4, pp. 419–424, 2000.
Y. Voronenko and M. Püschel, “Multiplierless multiple constant multiplication,” ACM Trans. Algorithms, vol. 3, no. 2, 2007, doi: 10.1145/ 1240233.1240234.
P. Cappello and K. Steiglitz, “Some complexity issues in digital signal Processing,” IEEE Trans. Acoust., Speech, Signal Process., vol. 32, no. 5, pp. 1037–1041, 1984.
R. Hartley, “Subexpression sharing in filters using canonic signed digit multipliers,” IEEE Trans. Circuits Syst. II, vol. 43, no. 10, pp. 677–688, 1996.
I.-C. Park and H.-J. Kang, “Digital filter synthesis based on minimal signed digit representation,” in Proc. Design Autom. Conf., 2001, pp. 468–473.
L. Aksoy,E. Costa, P. Flores, and J.Monteiro, “Exact and approximate algorithms for the optimization of area and delay in multiple constant Multiplications,” IEEE Trans. Comput.-Aided Design Intrgr. CircuitsSyst., vol. 27, no. 6, pp. 1013–1026, 2008.
A. Dempster and M. Macleod, “Use of minimumadder multiplierblocks in FIR digital filters,” IEEE Trans. Circuits Syst. II, vol. 42, no.9, pp. 569–577, 1995.
L. Aksoy, E. Gunes, and P. Flores, “Search algorithms for the multipleconstant multiplications problem: Exact and approximate,” Elsevier J.Microprocessors Microsyst., vol. 34, no. 5, pp. 151– 162, 2010.
K. Johansson, O. Gustafsson, and L. Wanhammar, “A detailed complexity model for multiple constant multiplication and an algorithm to minimize the complexity,” in Proc. IEEE Eur. Conf. Circuit Theory Design, 2005, pp. 465–468.
H.-J. Kang and I.-C. Park, “FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders,” IEEE Tran. on Circuits and Systems II, vol. 48, no. 8, pp. 770–777, 2001.
L. Aksoy, E. Costa, P. Flores, and J. Monteiro, “Finding the Optimal Tradeoff Between Area and Delay in Multiple Constant Multiplications,” Elsevier Journal on Microprocessors and Microsystems, vol. 35, no. 8, pp. 729–741, 2011.
Refbacks
- There are currently no refbacks.
Copyright © 2013, All rights reserved.| ijseat.com
International Journal of Science Engineering and Advance Technology is licensed under a Creative Commons Attribution 3.0 Unported License.Based on a work at IJSEat , Permissions beyond the scope of this license may be available at http://creativecommons.org/licenses/by/3.0/deed.en_GB.