Email this article A Reconfigurable Low Power FPGA Design with Autonomous Power Gating and LEDR Encoding
Abstract
In this project, design of an asynchronous FPGA blocks is implemented with power optimization techniques. Concentrated on STANDBY and DYNAMIC power consumptions are presented and studied on various gating techniques. Standby power is reduced by using autonomous fine grain power gating and reducing the dynamic power by using the level encoding dual rail (LEDR) architecture. The proposed autonomous fine grain power gating method each lookup table has its own sleep transistor and related sleep controller. So when any lookup tables are inactive, they can be set to sleep mode immediately. LEDR encoding is used to data flow at input and output of FPGAs, it reduces the dynamic power.
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References
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